Non-volatile (NV) memories can be widely used in many electronics applications to store data when power is not present. Examples of non-volatile memories include electrically programmable read only memories (EPROMs), such as ultraviolet (UV) erasable EPROMS, as well as electrically erasable non-volatile technologies including electrically erasable and programmable ROMs (EEPROMs), including “flash” EEPROMs, as well as magneto-resistive random access memories (MRAMs). These types of memories can be erased or written to a default state prior to being programmed for a given application. In some applications, technologies like those listed above may not be commercially viable, because they can be relatively expensive.
A different technology type that can be more cost effective than those listed above is anti-fuse technology. Anti-fuse technology can include an unprogrammed state the presents a very high impedance, and can be programmed to a lower impedance state. Thus, in a programmed state an anti-fuse device can draw some current, while in an unprogrammed state it can draw essentially no current. While very cost effective, anti-fuse devices can present great variability in resistance in the programmed state, presenting resistances that can vary by more than six orders of magnitude during normal operation. Alternatively, other arrangements can include fuses. Fuses include an unprogrammed state the presents a relatively low impedance, and can be programmed to a very high impedance state. Thus, in an unprogrammed state anti-fuse device can draw some current, while in a programmed state it can draw essentially no current. Anti-fuse and fuse technologies can be considered one-time programmable (OTP), as once they are programmed they may not be unprogrammed.
OTP technology can have various configurations, including “single-ended” OTP NV memory. Such a memory can include memory elements that can have a default state that is only selectively over-written. Another kind of non-volatile memory is a differential OTP NV memory. In a differential OTP memory element, two anti-fuse structures can have opposite states (one programmed, the other unprogrammed) to force a latch to a particular state. Single-ended OTP memory cells may not be as robust as differential OTP memory cells.
It can be desirable to test a NV memory device to determine if it is programmed. FIG. 11 shows a conventional circuit for testing a programming status of NV elements within memory device. Conventional circuit 1100 can include a validation key section 1102, an NV section 1104, a binary comparator circuit 1106, and control logic 1108. A validation key section 1102 can include circuits that provide a predetermined binary value KEY. Such a value KEY can be manufactured into a device, and thus be generated from a ROM circuit having values set by a manufacturing mask, or by laser programmed fuses, etc. A NV section 1104 can include a number of NV memory cells. Prior to being programmed, NV section 1104 can be expected to generate essentially random values. In contrast, when the memory device is programmed, memory cells within NV section 1104 can be programmed to store the value KEY.
In a test operation, a value provided by NV section 1104 can be compared to validation key KEY within comparator circuit 1106. If such values do not match, signal PRGD output from comparator circuit 1106 can be inactive, and the memory device can be determined to be not programmed. However, if such values do match, signal PRGD can be active, and the memory device can be determined to be programmed.
A second kind of conventional testing approach can be to manufacture a memory device having memory cells with NV element operating in conjunction with “weighted” latches. Weighted latches can be biased to latch to one logic value over the other. In such memory cells, absent a distinct programmed state, the memory cells will store a predetermined default logic value, determined by the latch weighting. In a test mode, memory cell values can be read, and if all are in the default state, the device can be determined to be non-programmed.
A disadvantage of conventional solutions that utilize “validation keys” is that while the probability of an unprogrammed device actually matching the key reduces dramatically with the number of bits, such a value is never zero. Thus, to help minimize such a risk, a validation key bit size can be increased. However, the larger the “validation key”, the more area that is required for the circuit. Still further, when such a device is programmed, a “validation key” must be programmed as well, and there is potential yield loss associated with each additional NV element that is programmed.
A disadvantage of conventional solutions that utilize weighted memory cells is that such circuit structures can be unreliable, requiring low defect densities and near perfect matching of multiple parameters to ensure proper operation.
It would be desirable to have a solution for determining if a NV memory was programmed or not that can be more robust and/or occupy less area than conventional solutions.
In addition, it is desirable to support memory elements whose programmed status presents resistance values that vary considerably, such as those of anti-fuse structures.